View CY7C1444AV33-1XWI_9092900.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

cy7c1444av33 36-mbit (1 m 36) pipelined dcd sync sram cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 38-05352 rev. *l revised november 2, 2012 36-mbit (1 m 36) pipelined dcd sync sram features supports bus operation up to 250 mhz available speed grades are 250 mhz and 167 mhz registered inputs and outputs for pipelined operation optimal for performance (double-cycle deselect) depth expansion wit hout wait state 3.3 v core power supply 2.5 v/3.3 v i/o power supply fast clock-to-output times ? 2.6 ns (for 250-mhz device) provide high-performance 3-1-1-1 access rate user-selectable burst counter supporting intel ? pentium ? interleaved or linear burst sequences separate processor and controller address strobes synchronous self-timed writes asynchronous output enable cy7c1444av33 available in jedec-standard pb-free 100-pin tqfp package ?zz? sleep mode option functional description the cy7c1444av33 sram integrates 1 m 36 sram cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. all synchronous inputs are gated by registers controlled by a positive-edge-triggered clock input (clk). the synchronous inpu ts include all addresses, all data inputs, address-pipelining chip enable (ce 1 ), depth-expansion chip enables (ce 2 and ce 3 ), burst control inputs (adsc , adsp , and adv ), write enables (bw x , and bwe ), and global write (gw ). asynchronous inputs include the output enable (oe ) and the zz pin. addresses and chip enables are registered at rising edge of clock when either address strobe processor (adsp ) or address strobe controller (adsc ) are active. subsequent burst addresses can be internally generated as controlled by the advance pin (adv ). address, data inputs, and write controls are registered on-chip to initiate a self-timed write cycle. this part supports byte write operations (see pin descriptions and truth table for further details). write cycles can be one to four bytes wide as controlled by the byte write control inputs. gw active low causes all bytes to be written. this device incorporates an additional pipelined enable register which delays turning off the output buffers an additional cycle when a deselect is executed. this feature allows depth expansion without p enalizing system performance. the cy7c1444av33 operates from a +3.3 v core power supply while all outputs operate with a +3.3 v or a +2.5 v supply. all inputs and outputs are jedec-standard jesd8-5-compatible. selection guide description 250 mhz 167 mhz unit maximum access time 2.6 3.4 ns maximum operating current 475 375 ma maximum cmos standby current 120 120 ma
cy7c1444av33 document number: 38-05352 rev. *l page 2 of 24 logic block diagram ? cy7c1444av33 address register adv clk burst counter and logic clr q1 q0 adsp adsc mode bw d bw c bw b bw a bwe gw ce 1 ce 2 ce 3 oe dq d, dqp d byte write register dq c ,dqp c byte write register dq b ,dqp b byte write register dq a, dqp a byte write register enable register pipelined enable output registers sense amps memory array output buffers dq a, dqp a byte write driver dq b ,dqp b byte write driver dq c ,dqp c byte write driver dq d, dqp d byte write driver input registers a0,a1,a a[1:0] sleep control zz e 2 dqs dqp a dqp b dqp c dqp d
cy7c1444av33 document number: 38-05352 rev. *l page 3 of 24 contents pin configurations ........................................................... 4 pin definitions .................................................................. 5 functional overview ........................................................ 6 single read accesses ................................................ 6 single write accesses initia ted by adsp ................... 6 single write accesses initiate d by adsc ................... 6 burst sequences ......................................................... 6 sleep mode ................................................................. 7 interleaved burst address tabl e ................................. 7 linear burst address table ......................................... 7 zz mode electrical characteri stics .............................. 7 truth table ........................................................................ 8 truth table for read/write .............................................. 9 maximum ratings ........................................................... 10 operating range ............................................................. 10 electrical characteristics ............................................... 10 capacitance .................................................................... 11 thermal resistance ........................................................ 11 ac test loads and waveforms ..................................... 12 switching characteristics .............................................. 13 switching waveforms .................................................... 14 ordering information ...................................................... 18 ordering code definitions ..... .................................... 18 package diagram ............................................................ 19 acronyms ........................................................................ 20 document conventions ................................................. 20 units of measure ....................................................... 20 document history page ................................................. 21 sales, solutions, and legal information ...................... 24 worldwide sales and design s upport ......... .............. 24 products .................................................................... 24 psoc solutions ......................................................... 24
cy7c1444av33 document number: 38-05352 rev. *l page 4 of 24 pin configurations figure 1. 100-pin tqfp (14 20 1.4 mm) pinout a a a a a 1 a 0 nc/72m a v ss v dd a a a a a a a a dqp b dq b dq b v ddq v ssq dq b dq b dq b dq b v ssq v ddq dq b dq b v ss nc v dd zz dq a dq a v ddq v ssq dq a dq a dq a dq a v ssq v ddq dq a dq a dqp a dqp c dq c dq c v ddq v ssq dq c dq c dq c dq c v ssq v ddq dq c dq c v dd nc v ss dq d dq d v ddq v ssq dq d dq d dq d dq d v ssq v ddq dq d dq d dqp d a a ce 1 ce 2 bw d bw c bw b bw a ce 3 v dd v ss clk gw bwe oe adsc adsp adv a a 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 mode cy7c1444av33 (1 m 36) nc a
cy7c1444av33 document number: 38-05352 rev. *l page 5 of 24 pin definitions name i/o description a 0 , a 1 , a input- synchronous address inputs used to select one of the address locations . sampled at the rising edge of the clk if adsp or adsc is active low, and ce 1 , ce 2 , and ce 3 are sampled active. a1:a0 are fed to the two-bit counter. bw a , bw b , bw c , bw d input- synchronous byte write select inputs, active low . qualified with bwe to conduct byte writes to the sram. sampled on the rising edge of clk. gw input- synchronous global write enable input, active low . when asserted low on the rising edge of clk, a global write is conducted (all bytes are writt en, regardless of the values on bw x and bwe ). bwe input- synchronous byte write enable input, ac tive low . sampled on the rising edge of clk. this signal must be asserted low to conduct a byte write. clk input- clock clock input . used to capture all synchronous inputs to the device. also used to increment the burst counter when adv is asserted low, during a burst operation. ce 1 input- synchronous chip enable 1 input, active low . sampled on the rising edge of clk. used in conjunction with ce 2 and ce 3 to select/deselect the device. adsp is ignored if ce 1 is high. ce 1 is sampled only when a new external address is loaded. ce 2 input- synchronous chip enable 2 input, active high . sampled on the rising edge of clk. used in conjunction with ce 1 and ce 3 to select/deselect the device. ce 2 is sampled only when a new external address is loaded. ce 3 input- synchronous chip enable 3 input, active low . sampled on the rising edge of clk. used in conjunction with ce 1 and ce 2 to select/deselect the device. ce 3 is sampled only when a new external address is loaded. oe input- asynchronous output enable, asynchronous input, active low . controls the direction of the i/o pins. when low, the i/o pins behave as outputs. when deasserted high, dq pins are tri-stated, and act as input data pins. oe is masked during the first clock of a read cycle when emerging fr om a deselected state. adv input- synchronous advance input signal, sampled on th e rising edge of clk, active low . when asserted, it automatically increments t he address in a burst cycle. adsp input- synchronous address strobe from processor, sampled on the rising edge of clk, active low . when asserted low, addresses presented to the device are captured in the address r egisters. a1: a0 are also loaded into the burst counter. when adsp and adsc are both asserted, only adsp is recognized. asdp is ignored when ce 1 is deasserted high. adsc input- synchronous address strobe from controller, sampled on the rising edge of clk, active low . when asserted low, addresses presented to the device are captured in the address registers. a1:a0 are also loaded into the burst counter. when adsp and adsc are both asserted, only adsp is recognized. zz input- asynchronous zz ?sleep? input, active high . when asserted high places the device in a non-time-critical ?sleep? condition with data integrity preserved. for normal op eration, this pin has to be low or left floating. zz pin has an internal pull-down. dqs, dqps i/o- synchronous bidirectional data i/o lines . as inputs, they feed into an on-chip data register that is triggered by the rising edge of clk. as outputs, they deliver the data contained in the memory location specified by the addresses presented during the previous clock rise of the read cycle. the direction of the pins is controlled by oe . when oe is asserted low, the pins behave as outputs. when high, dqs and dqp x are placed in a tri-state condition. v dd power supply power supply inputs to the core of the device . v ss ground ground for the core of the device . v ssq i/o ground ground for the i/o circuitry . v ddq i/o power supply power supply for the i/o circuitry . mode input- static selects burst order . when tied to gnd selects linear burst sequence. when tied to v dd or left floating selects interleaved burst sequence. this is a strap pi n and should remain static during device operation. mode pin has an internal pull-up. nc ? no connects . not internally connected to the die.
cy7c1444av33 document number: 38-05352 rev. *l page 6 of 24 functional overview all synchronous inputs pass through input registers controlled by the rising edge of the clock. all data outputs pass through output registers controlled by the ri sing edge of the clock. the cy7c1444av33 supports secondary cache in systems utilizing either a linear or interleaved burst sequence. the interleaved burst order supports pentium and i486 ? processors. the linear burst sequence is suited for processors that utilize a linear burst sequence. the burst order is user selectable, and is determined by sampling the mode input. accesses can be initiated with either the processor address strobe (adsp ) or the controller addre ss strobe (adsc ). address advancement through the burst sequence is controlled by the adv input. a two-bit on-chip wraparound burs t counter captures the first address in a burst sequence and automatically increments the address for the rest of the burst access. byte write operations are qualified with the byte write enable (bwe ) and byte write select (bw x ) inputs. a global write enable (gw ) overrides all byte write inputs and writes data to all four bytes. all writes are simplif ied with on-chip synchronous self-timed write circuitry. synchronous chip selects ce 1 , ce 2 , ce 3 and an asynchronous output enable (oe ) provide for easy bank selection and output tri-state control. adsp is ignored if ce 1 is high. single read accesses this access is initiated when the following conditions are satisfied at clo ck rise: (1) adsp or adsc is asserted low, (2) chip selects are all asserted active, and (3) the write signals (gw , bwe ) are all deasserted high. adsp is ignored if ce 1 is high. the address presented to the address inputs is stored into the address advancement logic and the address register while being presented to the memory core. the corresponding data is allowed to propagate to the input of the output registers. at the rising edge of the next clock the data is allowed to propagate through the output register and onto the data bus within t co if oe is active low. the only exception occurs when the sram is emerging from a deselected state to a selected state, its outputs are always tri-stated during the fi rst cycle of the access. after the first cycle of the access, the ou tputs are controlled by the oe signal. consecutive single read cycles are supported. the cy7c1444av33 is a double- cycle deselect part. once the sram is deselected at clock rise by the chip select and either adsp or adsc signals, its output will tri-state immediately after the next clock rise. single write accesses initiated by adsp this access is initiated when both of the following conditions are satisfied at clo ck rise: (1) adsp is asserted low, and (2) chip select is asserted active. the address presented is loaded into the address register and the address advancement logic while being delivered to the memory core. the write signals (gw , bwe , and bw x ) and adv inputs are ignored during this first cycle. adsp triggered write accesses require two clock cycles to complete. if gw is asserted low on th e second clock rise, the data presented to the dq x inputs is written into the corresponding address location in the memory core. if gw is high, then the write operation is controlled by bwe and bw x signals. the cy7c1444av33 provides byte write capability that is described in the write cycle description table. asserting the byte write enable input (bwe ) with the selected byte write input will selectively write to only the desired bytes. bytes not selected during a byte write operation will remain unaltered. a synchronous self-timed write me chanism has been provided to simplify the write operations. because the cy7c1444av33 is a common i/o device, the output enable (oe ) must be deasserted high before presenting data to the dq inputs. doing so will tri-state the output drivers. as a safety precaution, dq are automatically tr i-stated whenever a write cycle is detected, regardless of the state of oe . single write accesses initiated by adsc adsc write accesses are initiated when the following conditions are satisfied: (1) adsc is asserted low, (2) adsp is deasserted high, (3) chip select is asserted active, and (4) the appropriate combination of the write inputs (gw , bwe , and bw x ) are asserted active to conduct a wr ite to the desired byte(s). adsc triggered write accesse s require a single clock cycle to complete. the address presented is loaded into the address register and the address advancement logic while being delivered to the memory core. the adv input is ignored du ring this cycle. if a global write is conducted, the data presented to the dq x is written into the corresponding address location in the memory core. if a byte write is conducted, only the selected bytes are written. bytes not selected during a byte write operation will remain unaltered. a synchronou s self-timed write mechanism has been provided to simplify the write operations. because the cy7c1444av33 is a common i/o device, the output enable (oe ) must be deasserted high before presenting data to the dq x inputs. doing so will tri-state the output drivers. as a safety precaution, dq x are automatically tri-stated whenever a write cycle is detected, regardless of the state of oe . burst sequences the cy7c1444av33 provides a two-bit wraparound counter, fed by a [1:0] , that implements either an interleaved or linear burst sequence. the interleaved burst sequence is designed specifically to support intel pentium applications. the linear burst sequence is designed to support processors that follow a linear burst sequence. the burst sequence is user selectable nc/72m, nc/144m, nc/288m, nc/576m, nc/1g ? no connects . not internally connected to the die. 72 m, 144m, 288m, 576m and 1g are address expansion pins are not internally connected to the die. pin definitions (continued) name i/o description
cy7c1444av33 document number: 38-05352 rev. *l page 7 of 24 through the mode input. both read and write burst operations are supported. asserting adv low at clock rise will au tomatically increment the burst counter to the next addre ss in the burst sequence. both read and write burst ope rations are supported. sleep mode the zz input pin is an asynchronous input. asserting zz places the sram in a power conservation ?sleep? mode. two clock cycles are required to enter into or exit from this ?sleep? mode. while in this mode, data integrity is guaranteed. accesses pending when entering the ?sleep? mode are not considered valid nor is the completion of the o peration guaranteed. the device must be deselected prior to entering the ?sleep? mode. ce s, adsp , and adsc must remain inactive for the duration of t zzrec after the zz input returns low . interleaved burst address table (mode = floating or v dd ) first address a1:a0 second address a1:a0 third address a1:a0 fourth address a1:a0 00 01 10 11 01 00 11 10 10 11 00 01 11 10 01 00 linear burst address table (mode = gnd) first address a1:a0 second address a1:a0 third address a1:a0 fourth address a1:a0 00 01 10 11 01 10 11 00 10 11 00 01 11 00 01 10 zz mode electrical characteristics parameter description test conditions min max unit i ddzz sleep mode standby current zz > v dd ? ? 0.2 v ? 100 ma t zzs device operation to zz zz > v dd ? 0.2 v ? 2t cyc ns t zzrec zz recovery time zz < 0.2 v 2t cyc ?ns t zzi zz active to sleep current th is parameter is sampled ? 2t cyc ns t rzzi zz inactive to exit sleep current this parameter is sampled 0 ? ns
cy7c1444av33 document number: 38-05352 rev. *l page 8 of 24 truth table the truth table for cy7c1444av33 follows. [1, 2, 3, 4, 5, 6] operation add. used ce 1 ce 2 ce 3 zz adsp adsc adv write oe clk dq deselect cycle, power-down none h x x l x l x x x l?h tri-state deselect cycle, power-down none l l x l l x x x x l?h tri-state deselect cycle, power-down none l x h l l x x x x l?h tri-state deselect cycle, power-down none l l x l h l x x x l?h tri-state deselect cycle, power-down none l x h l h l x x x l?h tri-state sleep mode, power-down none x x x h x x x x x x tri-state read cycle, begin burst external l h l l l x x x l l?h q read cycle, begin burst external l h l l l x x x h l?h tri-state write cycle, begin burst external l h l l h l x l x l?h d read cycle, begin burst external l h l l h l x h l l?h q read cycle, begin burst external l h l l h l x h h l?h tri-state read cycle, continue burst next x x x l h h l h l l?h q read cycle, continue burst next x x x l h h l h h l?h tri-state read cycle, continue burst next h x x l x h l h l l?h q read cycle, continue burst next h x x l x h l h h l?h tri-state write cycle, continue burst next x x x l h h l l x l?h d write cycle, continue burst next h x x l x h l l x l?h d read cycle, suspend burst current x x x l h h h h l l?h q read cycle, suspend burst current x x x l h h h h h l?h tri-state read cycle, suspend burst current h x x l x h h h l l?h q read cycle, suspend burst current h x x l x h h h h l?h tri-state write cycle, suspend burst current x x x l h h h l x l?h d write cycle, suspend burst current h x x l x h h l x l?h d notes 1. x = ?don't care.? h = logic high, l = logic low. 2. write = l when any one or more byte write enable signals and bwe = l or gw = l. write = h when all byte write enable signals, bwe , gw = h. 3. the dq pins are controlled by the current cycle and the oe signal. oe is asynchronous and is not sampled with the clock. 4. ce 1 , ce 2 , and ce 3 are available only in the tqfp package. 5. the sram always initiates a read cycle when adsp is asserted, regardless of the state of gw , bwe , or bw x . writes may occur only on subsequent clocks after the adsp or with the assertion of adsc . as a result, oe must be driven high prior to the start of t he write cycle to allow the outputs to tri-state. oe is a don't care for the remainder of the write cycle. 6. oe is asynchronous and is not sa mpled with the clock rise. it is ma sked internally during write c ycles. during a read cycle all d ata bits are tri-state when oe is inactive or when the device is deselected, and a ll data bits behave as output when oe is active (low).
cy7c1444av33 document number: 38-05352 rev. *l page 9 of 24 truth table for read/write the truth table for read/write for cy7c1444av33 follows. [7, 8] function (cy7c1444av33) gw bwe bw d bw c bw b bw a read h h x x x x read hlhhhh write byte a ? (dq a and dqp a )hlhhhl write byte b ? (dq b and dqp b )hlhhlh write bytes b, a h l h h l l write byte c ? (dq c and dqp c )hlhlhh write bytes c, a h l h l h l write bytes c, b h l h l l h write bytes c, b, a h l h l l l write byte d ? (dq d and dqp d )hllhhh write bytes d, a h l l h h l write bytes d, b h l l h l h write bytes d, b, a h l l h l l write bytes d, c h l l l h h write bytes d, c, a h l l l h l write bytes d, c, b h l l l l h write all bytes hlllll write all bytes l x x x x x notes 7. the dq pins are controlled by the current cycle and the oe signal. oe is asynchronous and is not sampled with the clock. 8. table only lists a partial listing of the byte write combinations. any combination of bw x is valid appropriate write will be done based on which byte write is active.
cy7c1444av33 document number: 38-05352 rev. *l page 10 of 24 maximum ratings exceeding maximum ratings may shorten the useful life of the device. user guidelines are not tested. storage temperature .. ............... ............... ?65 c to +150 c ambient temperature with power applied ............ ............... ............... ?55 c to +125 c supply voltage on v dd relative to gnd .......?0.5 v to +4.6 v supply voltage on v ddq relative to gnd ...... ?0.5 v to +v dd dc voltage applied to outputs in tri-state ..........................................?0.5 v to v ddq + 0.5 v dc input voltage .............. .............. ..... ?0.5 v to v dd + 0.5 v current into outputs (low) ........................................ 20 ma static discharge voltage (per mil-std-883, method 3015) .............. ........... > 2001 v latch-up current ................................................... > 200 ma operating range range ambient temperature v dd v ddq commercial 0 c to +70 c 3.3 v ? ? 5% / + 10% 2.5 v ? 5% to v dd industrial ?40 c to +85 c electrical characteristics over the operating range parameter [9, 10] description test conditions min max unit v dd power supply voltage 3.135 3.6 v v ddq i/o supply voltage for 3.3 v i/o 3.135 v dd v for 2.5 v i/o 2.375 2.625 v v oh output high voltage for 3.3 v i/o, i oh = ?? 4.0 ma 2.4 ? v for 2.5 v i/o, i oh = ?? 1.0 ma 2.0 ? v v ol output low voltage for 3.3 v i/o, i ol = ? 8.0 ma ? 0.4 v for 2.5 v i/o, i ol = 1.0 ma ? 0.4 v v ih input high voltage [9] for 3.3 v i/o 2.0 v dd + 0.3 v for 2.5 v i/o 1.7 v dd + 0.3 v v il input low voltage [9] for 3.3 v i/o ?0.3 0.8 v for 2.5 v i/o ?0.3 0.7 v i x input leakage current except zz and mode gnd ? v i ? v ddq ?5 5 a input current of mode input = v ss ?30 ? a input = v dd ?5a input current of zz input = v ss ?5 ? a input = v dd ?30a i oz output leakage current gnd ? v i ? v ddq, output disabled ?5 5 a i dd v dd operating supply current v dd = max, i out = 0 ma, f = f max = 1/t cyc 4-ns cycle, 250 mhz -475ma 6-ns cycle, 167 mhz ?375ma notes 9. overshoot: v ih(ac) < v dd + 1.5 v (pulse width less than t cyc /2), undershoot: v il(ac) > ?2 v (pulse width less than t cyc /2). 10. t power-up : assumes a linear ramp from 0 v to v dd(min) within 200 ms. during this time v ih < v dd and v ddq < v dd .
cy7c1444av33 document number: 38-05352 rev. *l page 11 of 24 i sb1 automatic ce power-down current ? ttl inputs v dd = max, device deselected, v in ? v ih or v in ? v il , f = f max = 1/t cyc all speeds ? 225 ma i sb2 automatic ce power-down current ? cmos inputs v dd = max, device deselected, v in ? 0.3 v or v in > v ddq ? 0.3 v, f = 0 all speeds ? 120 ma i sb3 automatic ce power-down current ? cmos inputs v dd = max, device deselected, or v in ? 0.3 v or v in > v ddq ? 0.3 v, f = f max = 1/t cyc all speeds ? 200 ma i sb4 automatic ce power-down current ? ttl inputs v dd = max, device deselected, v in ? v ih or v in ? v il , f = 0 all speeds ? 135 ma electrical characteristics (continued) over the operating range parameter [9, 10] description test conditions min max unit capacitance parameter [11] description test conditions 100-pin tqfp max unit c in input capacitance t a = 25 ? c, f = 1 mhz, v dd = 3.3 v, v ddq = 2.5 v 6.5 pf c clk clock input capacitance 3pf c i/o input/output capacitance 5.5 pf thermal resistance parameter [11] description test conditions 100-pin tqfp package unit ? ja thermal resistance (junction to ambient) test conditions follow standard test methods and procedures for measuri ng thermal impedance, per eia/jesd51. 25.21 ? c/w ? jc thermal resistance (junction to case) 2.28 ? c/w note 11. tested initially and after any design or proc ess change that may affect these parameters.
cy7c1444av33 document number: 38-05352 rev. *l page 12 of 24 ac test loads and waveforms figure 2. ac test loads and waveforms output r = 317 ? r = 351 ? 5pf including jig and scope (a) (b) output r l = 50 ? z 0 = 50 ? v t = 1.5 v 3.3 v all input pulses v ddq gnd 90% 10% 90% 10% ? 1 ns ? 1 ns (c) output r = 1667 ? r = 1538 ? 5pf including jig and scope (a) (b) output r l = 50 ? z 0 = 50 ? v t = 1.25 v 2.5 v all input pulses v ddq gnd 90% 10% 90% 10% ? 1 ns ? 1 ns (c) 3.3 v i/o test load 2.5 v i/o test load
cy7c1444av33 document number: 38-05352 rev. *l page 13 of 24 switching characteristics over the operating range parameter [12, 13] description -250 -167 unit min max min max t power v dd (typical) to the first access [14] 1 ? 1 ? ms clock t cyc clock cycle time 4 ? 6 ? ns t ch clock high 1.5 ? 2.4 ? ns t cl clock low 1.5 ? 2.4 ? ns output times t co data output valid after clk rise ? 3.4 ? 3.4 ns t doh data output hold after clk rise 1.0 ? 1.5 ? ns t clz clock to low z [15, 16, 17] 1.0 ? 1.5 ? ns t chz clock to high z [15, 16, 17] ? 3.4 ? 3.4 ns t oev oe low to output valid ? 3.4 ? 3.4 ns t oelz oe low to output low z [15, 16, 17] 0 ? 0 ? ns t oehz oe high to output high z [15, 16, 17] ? 3.4 ? 3.4 ns set-up times t as address set-up before clk rise 1.2 ? 1.5 ? ns t ads adsc , adsp set-up before clk rise 1.2 ? 1.5 ? ns t advs adv set-up before clk rise 1.2 ? 1.5 ? ns t wes gw , bwe , bw x set-up before clk rise 1.2 ? 1.5 ? ns t ds data input set-up before clk rise 1.2 ? 1.5 ? ns t ces chip enable set-up before clk rise 1.2 ? 1.5 ? ns hold times t ah address hold after clk rise 0.3 ? 0.5 ? ns t adh adsp , adsc hold after clk rise 0.3 ? 0.5 ? ns t advh adv hold after clk rise 0.3 ? 0.5 ? ns t weh gw , bwe , bw x hold after clk rise 0.3 ? 0.5 ? ns t dh data input hold after clk rise 0.3 ? 0.5 ? ns t ceh chip enable hold after clk rise 0.3 ? 0.5 ? ns notes 12. timing reference level is 1.5 v when v ddq = 3.3 v and is 1.25 v when v ddq = 2.5 v. 13. test conditions shown in (a) of figure 2 on page 12 unless otherwise noted. 14. this part has a voltage regulator internally; t power is the time that the power needs to be supplied above v dd(minimum) initially before a read or write operation can be initiated. 15. t chz , t clz ,t oelz , and t oehz are specified with ac test conditions shown in part (b) of figure 2 on page 12 . transition is measured 200 mv from steady-state voltage. 16. at any given voltage and temperature, t oehz is less than t oelz and t chz is less than t clz to eliminate bus contention between srams when sharing the same data bus. these specificati ons do not imply a bus contention condition, but refl ect parameters guaranteed over worst case user condi tions. device is designed to achieve high z prior to low z under the same system conditions. 17. this parameter is sampled and not 100% tested.
cy7c1444av33 document number: 38-05352 rev. *l page 14 of 24 switching waveforms figure 3. read cycle timing [18] t cyc t cl clk adsp t adh t ads address t ch oe adsc ce t ah t as a1 t ceh t ces gw, bwe,bw data out (dq) high-z t doh t co adv t oehz t co single read burst read t oev t oelz t chz burst wraps around to its initial state t advh t advs t weh t wes t adh t ads q(a2) q(a2 + 1) q(a2 + 2) q(a1) q(a2) q(a2 + 1) q(a3) q(a2 + 3) a2 a3 deselect cycle burst continued with new base address adv suspends burst don?t care undefined x clz t note 18. on this diagram, when ce is low: ce 1 is low, ce 2 is high and ce 3 is low. when ce is high: ce 1 is high or ce 2 is low or ce 3 is high.
cy7c1444av33 document number: 38-05352 rev. *l page 15 of 24 figure 4. write cycle timing [19, 20] switching waveforms (continued) t cyc t cl clk adsp t adh t ads address t ch oe adsc ce t ah t as a1 t ceh t ces bwe, bw x adv burst read burst write d(a2) d(a2 + 1) d(a2 + 1) d(a3) d(a3 + 1) d(a3 + 2) d(a2 + 3) a2 a3 extended burst write d(a2 + 2) single write t adh t ads t adh t ads t oehz t advh t advs t weh t wes t dh t ds gw t weh t wes byte write signals are ignored for first cycle when adsp initiates burst adsc extends burst adv suspends burst don?t care undefined d(a1) high-z data in (d) data out (q) notes 19. on this diagram, when ce is low: ce 1 is low, ce 2 is high and ce 3 is low. when ce is high: ce 1 is high or ce 2 is low or ce 3 is high. 20. full width write can be initiated by either gw low; or by gw high, bwe low and bw x low.
cy7c1444av33 document number: 38-05352 rev. *l page 16 of 24 figure 5. read/write cycle timing [21, 22, 23] switching waveforms (continued) t cyc t cl clk adsp t adh t ads address t ch oe adsc ce t ah t as a2 t ceh t ces data out (q) high-z adv single write d(a3) a4 a5 a6 d(a5) d(a6) data in (d) burst read back-to-back reads high-z q(a2) q(a1) q(a4) q(a4+1) q(a4+2) t weh t wes q(a4+3) t oehz t dh t ds t oelz t clz t co back-to-back writes a1 bwe, bw x a3 don?t care undefined notes 21. on this diagram, when ce is low: ce 1 is low, ce 2 is high and ce 3 is low. when ce is high: ce 1 is high or ce 2 is low or ce 3 is high. 22. the data bus (q) remains in high z following a write cycle, unless a new read access is initiated by adsp or adsc . 23. gw is high.
cy7c1444av33 document number: 38-05352 rev. *l page 17 of 24 figure 6. zz mode timing [24, 25] switching waveforms (continued) t zz i supply clk zz t zzrec all inputs (except zz) don?t care i ddzz t zzi t rzzi outputs (q) high-z deselect or read only notes 24. device must be deselected when entering zz mode. see cycle de scriptions table for all possible signal conditions to deselect the device. 25. dqs are in high z when exiting zz sleep mode.
cy7c1444av33 document number: 38-05352 rev. *l page 18 of 24 ordering code definitions ordering information cypress offers other versions of this type of product in many different configurati ons and features. the below table contains o nly the list of parts that are currently available. for a co mplete listing of all options , visit the cypress website at www.cypress.com and refer to the product summary page at http://www.cypress.com/products or contact your local sales representative. cypress maintains a worldwide network of offices, solution centers, manuf acturer?s representatives and distributors. to find the office closest to you, visit us at http://www.cypress.com/ go/datasheet/offices . speed (mhz) ordering code package diagram part and package type operating range 250 cy7c1444av33-250axi 51-85050 100-pin tqfp (14 20 1.4 mm) pb-free industrial 167 cy7c1444av33-167axc 51-85050 100-pin tqfp (14 20 1.4 mm) pb-free commercial temperature range: x = i or c i = industrial; c = commercial pb-free package type: a = 100-pin tqfp frequency range: xxx = 250 mhz or 167 mhz v33 = 3.3 v process technology: a ? 90 nm part identifier: 1444 = dcd, 1 mb 36 (36 mb) technology code: c = cmos marketing code: 7 = sram company id: cy = cypress c 1444 a - xxx x x v33 cy a 7
cy7c1444av33 document number: 38-05352 rev. *l page 19 of 24 package diagram figure 7. 100-pin tqfp (14 20 1.4 mm) a100ra package outline, 51-85050 51-85050 *d
cy7c1444av33 document number: 38-05352 rev. *l page 20 of 24 acronyms document conventions units of measure acronym description ce chip enable cmos complementary metal oxide semiconductor eia electronic industries alliance i/o input/output jedec joint electron devices engineering council lsb least significant bit msb most significant bit oe output enable sram static random access memory tqfp thin quad flat pack ttl transistor-transistor logic symbol unit of measure c degree celsius mhz megahertz a microampere ma milliampere mm millimeter ms millisecond mv millivolt nm nanometer ns nanosecond ? ohm % percent pf picofarad vvolt wwatt
cy7c1444av33 document number: 38-05352 rev. *l page 21 of 24 document history page document title: cy7c1444av33, 36-mbit (1 m 36) pipelined dcd sync sram document number: 38-05352 rev. ecn no. submission date orig. of change description of change ** 124419 03/04/03 cgm new data sheet. *a 254910 see ecn syt updated logic block diagram ? cy7c1444av33. updated logic block diagram ? cy7c1445av33. updated identification register definition s (added note ?bit #24 is ?1? in the id register definitions for both 2.5 v a nd 3.3 v versions of this device.? and referred the same in device depth (28:24)). added boundary scan order related information. updated electrical characteristics (updated values of i dd , i x and i sb parameters). updated switching characteristics (added t power parameter and its details). updated switching waveforms . updated package diagram (removed 119-ball pbga package, changed 165-ball fbga package from bb165c (15 17 1.20 mm) to bb165 (15 17 1.40 mm)). *b 303533 see ecn syt updated electrical characteristics (changed test condition from v dd = min. to v dd = max for v ol parameter, changed maximum value of i dd from 450 ma, 400 ma, and 350 ma to 475 ma, 425 ma, and 375 ma for 250 mhz, 200 mhz, and 167 mhz frequencies respectively, changed maximum value of i sb1 parameter from 190 ma, 180 ma, and 170 ma to 225 ma for 250 mhz, 200 mhz, and 167 mhz frequencies respectively, changed maximum value of i sb2 parameter from 80 ma to 100 ma for all frequencies, changed maximum value of i sb3 from 180 ma, 170 ma, and 160 ma to 200 ma for 250 mhz, 200 mhz, and 167 mhz respectively, changed maximum value of i sb4 parameter from 100 ma to 110 ma for all frequencies). updated capacitance (changed value of c in , c clk and c i/o to 6.5 pf, 3 pf, and 5.5 pf from 5 pf, 5 pf, and 7 pf for 100-pin tqfp package). updated thermal resistance (replaced values of ? ja and ? jc parameters from tbd to respective thermal values for all packages). updated switching characteristics (changed maximum value of t co parameter from 3.0 ns to 3.2 ns for 200 mhz frequency, changed minimum value of t doh parameter from 1.3 ns to 1.5 ns for 200 mhz frequency). updated ordering information (added lead-free information for 100-pin tqfp and 165-ball fbga packages). *c 331778 see ecn syt updated pin configurations (modified address expansion balls in the pinouts for 165-ball fbga package as per jedec standards). updated pin definitions . updated operating range (added industrial temperature range). updated electrical characteristics (updated test conditions of v ol, v oh parameters, changed maximum value of i sb2 and i sb4 parameters from 100 ma and 110 ma to 120 ma and 135 ma respectively). updated capacitance (changed value of c in , c clk and c i/o to 7 pf, 7 pf, and 6 pf from 5 pf, 5 pf, and 7 pf for 165-ball fbga package). updated ordering information (by shading and unshading mpns as per availability).
cy7c1444av33 document number: 38-05352 rev. *l page 22 of 24 *d 417509 see ecn rxu changed status from preliminary to final. changed address of cypress semicondu ctor corporation from ?3901 north first street? to ?198 champion court?. updated electrical characteristics (updated note 10 (modified test condition from v ih < v dd to v ih ?? v dd ), changed ?input load cu rrent except zz and mode? to ?input leakage current except zz and mode?, changed minimum value of i x corresponding to input current of mode (input = v ss ) from ?5 ? a to ?30 ? a, changed maximum value of i x corresponding to input current of mode (input = v dd ) from 30 ? a to 5 ? a respectively, changed minimum value of i x corresponding to input current of zz (input = v ss ) from ?30 ? a to ?5 ? a, changed maximum value of i x corresponding to input current of zz (input = v dd ) from 5 ? a to 30 ? a). updated ordering information (replaced package name column with package diagram in the ordering information table). updated package diagram (spec 51-85050 (changed revision from *a to *b)). *e 473229 see ecn vkn updated tap ac switching characteristics (changed minimum value of t th , t tl parameters from 25 ns to 20 ns, changed maximum value of t tdov parameter from 5 ns to 10 ns). updated maximum ratings (added the maximum rating for supply voltage on v ddq relative to gnd). updated ordering information (updated part numbers). *f 2898663 03/24/2010 njy updated ordering information (removed inactive parts). updated package diagram . *g 3042209 09/29/2010 njy added ordering code definitions . added acronyms and units of measure . minor edits and updated in new template. *h 3263545 05/23/2011 njy updated package diagram . *i 3363203 09/05/2011 prit updated in new template. document history page (continued) document title: cy7c1444av33, 36-mbit (1 m 36) pipelined dcd sync sram document number: 38-05352 rev. ecn no. submission date orig. of change description of change
cy7c1444av33 document number: 38-05352 rev. *l page 23 of 24 *j 3616631 05/14/2012 prit updated features (removed 250 mhz, 200 mhz frequencies related information, removed cy7c1445av33 related information, removed 165-ball fbga package related information). updated functional description (removed cy7c1445av33 related information, removed the note ?for be st-practices recommendations, please refer to the cypress application note system design guidelines on www.cypress.com .? and its reference). updated selection guide (removed 250 mhz, 200 mhz frequencies related information). removed logic block diagram ? cy7c1445av33. updated pin configurations (removed cy7c1445av33 related information, removed 165-ball fbga package related information). updated pin definitions (removed jtag related information). updated functional overview (removed cy7c1445av33 related information). updated truth table (removed cy7c1445av33 related information). removed truth table for read/write (corresponding to cy7c1445av33). removed ieee 1149.1 serial boundary scan (jtag). removed tap controller state diagram. removed tap controller block diagram. removed tap timing. removed tap ac switching characteristics. removed 3.3 v tap ac test conditions. removed 3.3 v tap ac output load equivalent. removed 2.5 v tap ac test conditions. removed 2.5 v tap ac output load equivalent. removed tap dc electrical charac teristics and operating conditions. removed identification register definitions. removed scan register sizes. removed instruction codes. removed boundary scan order. updated operating range (removed industrial temperature range). updated electrical characteristics (removed 250 mhz, 200 mhz frequencies related information). updated capacitance (removed 165-ball fbga package related information). updated thermal resistance (removed 165-ball fbga package related information). updated switching characteristics (removed 250 mhz, 200 mhz frequencies related information). *k 3753416 09/24/2012 prit no technical updates. completing sunset review. *l 3800874 11/02/2012 prit updated features (included 250 mhz frequen cy related information). updated selection guide (included 250 mhz frequency related information). updated operating range (included industrial temperature range). updated electrical characteristics (included 250 mhz frequency related information). updated switching characteristics (included 250 mhz frequency related information). updated ordering information (updated part numbers). document history page (continued) document title: cy7c1444av33, 36-mbit (1 m 36) pipelined dcd sync sram document number: 38-05352 rev. ecn no. submission date orig. of change description of change
document number: 38-05352 rev. *l revised november 2, 2012 page 24 of 24 i486 is a trademark, and intel and pentium are registered trademarks of intel corporation. all products and company names menti oned in this document may be the tr ademarks of their respective holders. cy7c1444av33 ? cypress semiconductor corporation, 2003-2012. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory optical & image sensing cypress.com/go/image psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 5

▲Up To Search▲

Price & Availability of CY7C1444AV33-1XWI

	To Download CY7C1444AV33-1XWI Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .